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application note an 2012 - 04 v 1 . 0 april 2012 5 0 0 v c o o l m o s tm ce 5 0 0 v s u p e r j u n c t i o n m o s f e t f o r c o n s u m e r a n d l i g h t i n g a p p l i c a t i o n s ifat pmm aps se sl ren mente francesco di domenico
500v coolmos tm ce 2 application note an 20 12 - 04 v 1 . 0 april 20 12 edition 2011 - 0 2 - 02 published by infineon technologies austria ag 9500 villach, austria ? infineon technologies austria ag 2012 all rights reserved. attention please ! the information given in this application note is given as a hint for the implemen - tation of the infineon technologies component only and shall not be regarded as any description or warranty of a certain functionality, condition or quality of the infineon technologies component. the recipient of this application note must verify any function described herein in the real application. infineon technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warran ties of non - infringement of intellectual property rights of any third party) with respect to any and all information given in this application note. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life - support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. an 20 12 - 04 revision history: date ( 12 - 04 - 20 ) , v 1 . 0 previous version: none subjects: 1 st revision authors: ifat pmm aps se sl ren mente francesco di domenico we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: [ rene.mente@infineon.com ]
500v coolmos tm ce 3 application note an 20 12 - 04 v 1 . 0 april 20 12 table of contents 1 introduction ................................ ................................ ................................ ................................ .................. 4 1.1 features and benefits ................................ ................................ ................................ ........................ 4 1.2 applications (target market) ................................ ................................ ................................ .............. 5 2 superjunction (sj) principle ................................ ................................ ................................ ...................... 5 2.1 general description ................................ ................................ ................................ ........................... 5 2.2 supe rjunction benefit of 500v ce ................................ ................................ ................................ ..... 7 2.2.1 switching speed ................................ ................................ ................................ ............................ 7 2.2.2 bjt (bipolar junction transistor) - effect ................................ ................................ ........................ 9 3 technology parameters ................................ ................................ ................................ ............................ 11 3.1 gate charge (q g ) ................................ ................................ ................................ ............................. 11 3.2 energy stored in output capacitance (e oss ) ................................ ................................ .................... 12 4 measurement results ................................ ................................ ................................ ............................... 13 4.1 efficiency in ccm pfc ................................ ................................ ................................ .................... 13 4.2 hard commutation on conducting body diode ................................ ................................ ............... 15 5 design guideline for using 500v ce ................................ ................................ ................................ ....... 16 5.1 minimum external gate resistor (r g,ext ) ................................ ................................ ......................... 16 5.2 paralleling of 500v ce ................................ ................................ ................................ ..................... 16 5.3 safe operation after protection mode ................................ ................................ ............................. 17 6 portfolio ................................ ................................ ................................ ................................ ...................... 19 7 references ................................ ................................ ................................ ................................ ................. 20
500v coolmos tm ce 4 application note an 20 12 - 04 v 1 . 0 april 20 12 1 introduction the new coolmos tm ce is the fourth technology platform of infineons market leading high voltage power mosfets designed according to the revolutionary superjunction (sj) principle in the 500v class . 500v ce portfolio pr o vides all benefits of a fast switching superjunction ( sj ) mosfet while keeping ease of use and implementation. t he complete ce series of mosfets achieve very low conduction and switching losses , and can make applications more efficient, more compact, lighter and thermally cooler . this application note will describe the fundamental differences between a sj mosfet and a standard mosfet. additionally, all features and benefits impacting the target applications will be described . furthermore, these features will be illustrated from both a theoretical point of vi ew and in hardware measurements. it will also be shown that coolmos tm ce is a cost effective alternative compared to standard mosfets , which enables reach ing higher efficiency levels while offering an attractive price / performance ratio. 1.1 features and benefi ts the following table represents the features and benefits of coolmos tm ce i n comparison to standard mosfet s, which will be discussed in depth in the main part of this application note . table 1 : features and benefits feature s benefits r educed energy stored in output capacitance (e oss ) r eduction of switching losses , improvement of light load efficiency h igh body diode ruggedness h igher reliability under critical operating conditions r educed reverse recover y charge (q rr ) l ower possibility of hard commutation in resonant topologies r educed gate charge (q g ) i mprovement in light load efficiency lower gate drive capability required o verall features e asy control of switching behavior o utstanding reliability with proven coolmos tm quality
500v coolmos tm ce 5 application note an 20 12 - 04 v 1 . 0 april 20 12 1.2 applications ( t arget m arket) the following table represents the target applications and topologies for these new mosfets. table 2 : target applications and topologies application pfc pwm pc silverbox boost - stage ttf llc lcd / led / pdp tv boost - stage llc gaming boost - stage ttf llc lighting boost - stage llc all the features and benefits of the 500v ce in connection with the target applications and topologies will be analyzed in section 4 . the following section will describe the differences between sj mosfet s and standard mosfet s . 2 superjunction (sj) principle in the past the consumer market has been dominated by standard mosfets. therefore this chapter is included to show the difference to sj mosfets. 2.1 gen eral description all coolmos tm series are based on the s uperjunction principle, which is a revolutionary technology for high voltage power mosfets [1, 2] , infineon technologies has been the first company worldwide to commercialize this idea int o the market [4] . where conventional power mosfets just command on one degree of freedom to master both on - state resist ance and blocking voltage, the s uperjunction principle allows t w o degree s of freedom for this task. therefore conventional mosfets are st uck with the limit of silicon, a barrier which marks the optimum doping profile for a given voltage class. this limit line has been theoretically derived by chen and hu in the late 80ies [3] . no commercial product has an on - state resistance better than the limit line of silicon. [5] figure 1 represents the area - specific on - resistance versus breakdown voltage.
500v coolmos tm ce 6 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 1 : area - specific on - resistance versus breakdown voltage comparison of standard mosfet an d coolmos tm technology [6] in contrast to that the s uperjunction principle allows to reduce the on - state resistance of a high voltage mosfet virtually to z ero, limited only by technology efforts and manufacturing capabilities. [ 5 ] the basic idea is simple: instead of having electrons flowing through a relative ly high resistive (high voltage blocking) n - area, we allow them to flow in a very rich doped n - area, which give s naturally a very low on - state resistance. the crucial point for the sj technology is to make the device block i ts full voltage, which requires a careful balancing of the additional n - charge by adjacently positioned deep p - columns, which go all the way straight through the device close to the back side n+ contact. this is where manufact uring capability comes in, as the charges within the device need to be compensated precisely under the constraints of a mass market p roduction line. [5] figure 2 sho ws the cross section of a standard mosfet (left) and a sj mosfet (right). 0.00 10.00 20.00 30.00 40.00 500 600 700 800 900 1000 area specific resistance [ ? *mm 2 ] blocking voltage [v] coolmos tm state - of the - art conventional mos "silicon limit"
500v coolmos tm ce 7 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 2 : cross section of standard mosfet (left) and sj mosfet (right) [5] the sj principle gives us the opportunity to create best - in - class types, which have not been possible before such as a 100 m/600v part in a to - 220 package. furthermore it allows making parts with very low capacitances for a given r ds(on) as the silicon chip is much smaller than for a conventional power mosfet. both input and h igh voltage level of the output capacitance scale directly with the chip size, whereas reverse capacitance and to some extent the low voltage level of the output capacitance is technology dependent. characteristic of all superjunction devices is a strong n on - linearity of the output capacitance with high values at low voltage and low values at high voltage. this behavior can be easily understood if you take into account that the output capacitance is proportional to the area of the blocking pn - junction and i nverse proportional to the width of the space charge layer (or the voltage sustaining area). at low voltage the p - columns are not depleted and form a very big surface, furthermore the width of the space charge layer is very narrow (the white area seen in figure 2 ) . at high voltage however the p - columns are fully depleted and the space charge layer has reached its full extension of roughly 45m for a 600v device. important is that the non - linearity o f the output capacitance allows a quasi zero - voltage - switching (zvs) turn - off of the device, lowering turn - off losses. superjunction devices are by nature fast in switching. very small capacitances together with a low gate charge make rise and fall times o f a few nanoseconds a reality. [5] for more information on s uperjunction devices please read the article maste ring the art of slowness which is available on www.infineon.com. 2.2 superjunction benefit of 500v ce chapter 2.1 illustrated the genera l characteristics of a sj mosfet in comparison to a standard mosfet . n ow the question arises what is the benefit for the 500v ce? this application note will describe two of the most important factors starting with the switching speed. 2.2.1 switchi ng speed as mentioned in the general description the switching speed increases dramatically. this behavior comes from the low parasitic capacitances of a sj mosfet in comparison to the standard mosfet. a sj mosfet has about half of the value of input and output capacitance , which brings the benefit s for switching losses and driving losses. figure 3 represents these parasitic capacitances (marked in red) in a simplified schematic .
500v coolmos tm ce 8 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 3 : simplified small signal mosfet equivalent ci rcuit because of this capacitance reduction the e on and e off of the 500v ce is about half in comparison to a standard mosfet . furthermore this reduction of capacitances results also in a reduced gate charge q g which gives the benefit of reduc ed driving losses , and the possibility to use a lower cost driver w ith less gate drive capability. figure 4 represents the capacitance comparison of the 500v ce (280mohm) vs . a comparable standard mosfet. figure 4 : capacitance comparison 500v ce vs. standard mosfet 1 10 100 1000 10000 0 100 200 300 400 500 c iss , c oss , c rss [pf] v ds [v] capacitances ipa50r280ce vs. standard mosfet ipa50r280ce ciss ipa50r280ce coss ipa50r280ce crss standard mos ciss standard mos coss standard mos crss
500v coolmos tm ce 9 application note an 20 12 - 04 v 1 . 0 april 20 12 a fundamental characteristic of all superjunction devices is, that both the output and reverse capacitance show a strong non - linearity. the non - linearity in superjunction capacitance characteristics comes from the fact that at a given voltage C typically i n the range of 1/10th of the rated blocking voltage C p - and n - columns deplete each other leading to a fast expansion of the space charge layer throughout the structure. this means that at a voltage beyond 5 0v for 5 00v rated devices both output and reverse capacitance reach minimum values of a few pf only, resulting in a dv/dt of more than 100v/ns and di/dt of several thousand a/s if the load current is allowed to fully commute into the output capacitance during turn - off. the output capacitance is charged up to the level of the bus voltage where the voltage rise follows then the formula: (1) the voltage rise is therefore proportional to the load current i load and inverse proportional to the value of the output capacitance c oss . because of the decreasing c oss towards higher voltages, the highest dv/dt is reached shortly before reaching the bus voltage. the according di/dt is mainly limited by the inductances of package and pcb circuit. the highest efficiency can now be reached by turning - off the device in this manner, because the occurring switching losses can be ideally reduced down to the level of the stored energy in the output capacitance. [7] all these benefits wil l be clearly visible in the efficiency results, which will be described in chapter 4 . the second difference is the so called bjt - effect. 2.2.2 bjt (bipolar junction transistor) - effect if the body diode conducts in forward direction, minority carriers remaining in the base region during diode recovery can cause a bjt a ction with destructive results (short circuit of drain source while high voltages are applied) . how is it possible to trigger the bjt - effect? this is shown step by step in the following: in a zero voltage switching topology the forward current (i sd ) is fo rced into the body diode to clamp the output at e i ther the positive or negative rail following a current driven drain to source transition . this forward current causes the generation of minority carriers in both the p doped body (electrons) and n epi region s (holes). oss load c i dt dv ? /
500v coolmos tm ce 10 application note an 20 12 - 04 v 1 . 0 april 20 12 the mosfet channel is turned on and diverts a portion of the current through the channel away from the body diode, that is still forward conducting (mosfet can conduct current in both directions). this lower current flowing through the body diode will reduce the generation of minority carriers but will not stop it . the external circuitry reverses the current flow through the device - > small amount of reverse current flows in body diode (small due to the very weak voltage generated by very low current flowing in the low resistive channel, especially at light load operation ). some minority carrie rs will be removed from the p - n - junction, but not all due to a conduction period that is short in relation to the intrinsic carrier lifetime . if the mosfet completely turns on the current will be completely diverted to the channel, but if the mosfet turns off when there are still minority carriers in the b ody diode the fol lowing happens: the mosfet will begin to block voltage imposing a higher reverse voltage on the body diode, with high dv/dt. the application of high reverse voltage on the body diode will sweep the remaining carriers across the junction very quickly . minor ity carriers in the n epi region are swept towards the p+ body. - > if this current (flowing into r b , represented in figure 5 ) reaches a magnitude sufficient to activate the intrinsic bipolar transistor, second breakdown will occur destroying the mosfet. in a conventional mosfet the hole current, fed by reverse recovery charge, flow laterally into the p doped region crossing the area below the n region before they reach the top side of the device below the gate electrode: so this current flows through r b of the parasitic bipolar structure , with the risk of forward biasing of npn - junction and consequent triggering of parasitic bjt.
500v coolmos tm ce 11 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 5 : bjt - effect as visible in f igure 5 (right) in a coolmos tm the hole current flows upwards through the p doped column, before it reach es the metalized contact, but no lateral current will pass through the p doped well and therefore no current flows through r b reducing the possibility of trigger ing the bjt - effect to nearly zero. now that the basics of the sj mosfet have been discussed, thi s paper is going to continue with technology parameters and their influence on the applications in the specific topologies. 3 technology parameters 3.1 gate charge (q g ) one of the most important improvements is the q g reduction which brings benefits especially in light load conditions due to reduced driving losses. in general the 500v ce has about 40% q g reduction in comparison to an comparable standard mosfet over the whole r ds(on) range. figure 6 s hows the q g in nc of the 500v ce against a standard mos fet over the r ds(on) ,max range from 190m ? to 950m ? .
500v coolmos tm ce 12 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 6 : q g comparison 500v ce vs. standard mosfet 3.2 energy stored in output capacitance (e oss ) the reduced energy stored in the output capacitance brings the most important difference in hard switching topologies but nevertheless it affects also the switching losses in a resonant topology. normally it is possible to choose between zero voltage switching (zvs) or zero current switching (zcs). in these two cases it is possible to eliminate the turn - on losses (zvs) or the turn - off losses (zcs) , but it is not possible to work in these two operation modes at the same time. normally for mosfets the zvs operation is preferred due to the usually important contribution of the output capacitance to the turn - on losses (if hard switching). therefor e , one part of the switching losses is still always in action and the reduction of e oss brings a reduction of those switching losses. figure 7 represents the e oss com parison between the 500v ce and a comparable standard mosfet of the 500m ? devices. ~40% q g reduction 0 50 100 150 200 250 300 350 0 200 400 600 800 1000 q g [nc] r ds(on),max [m ?] 500v ce vs. standard mos typical q g * r ds(on),max [nc* ? ] 500v ce standard mos
500v coolmos tm ce 13 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 7 : e oss comparison 500v ce vs. standard mosfet the e oss loss is in direct proportion to the output capacitance as a function of drain to source voltage of the mosfet. in this case the effect of a reduction of c oss is clearly visible . one further benefit out of this is a faster v ds transition time in resonant topologies , which mean s that it is possible to redu ce the resonant inductance and circulating current loss, because it is possible to completely discharge the c oss with lower currents. 4 measurement results in order to show the impact of the mentioned tec hnology parameters this section will describe some measurements starting with the efficiency comparison in a ccm pfc , which is one of the most suitable topolog ies to verify the new mosfets in hard switching . 4.1 efficiency in ccm pfc in this measurement the 500v ce is compared to a comparable standard mos fet in the 280m ? r ds(on) range. setup parameters: ? ccm pfc ? v in =90vac ? v out =400vdc ? p out =0w to 400w ? frequency=100khz ? r g,ext =5 ? ? ambient temperature 25c ? heat sink temperature preheated to 60c ? plug and play scenario between 500v ce and standard mosfet 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 e oss [j] v ds [v] ipp50r500ce vs. standard mos e oss comparison of 500mohm devices ipp50r500ce standard mos
500v coolmos tm ce 14 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 8 : 500v ce vs. standard mosfet comparison in absolute efficiency (upper) and delta efficiency (lower) this plug and play measurement shows the benefit of a sj mosfet in comparison to a standard mosfet. in light load conditi on (~40w) . d ue to the q g reduction an efficiency difference in light load operation (~40w) of more than 0.9% is visible. the efficiency of the ipp50r280ce is on average 0.4% higher than the comparable standard mosfet over the whole load range. here also the effect s of the lower e on and e off are visible. figure 9 represents the e on and e off values of an ipa50r500ce in comparison to a com parable standard mosfet over r g,ext at different drain currents (i d ) and test ambient temperature ( t c ) of 25c.
500v coolmos tm ce 15 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 9 : e on and e off comparison ipa50r500ce vs. standard mosfet at i d =2.93a (upper) and i d =5.85a (lower) it is shown that the e on and e off are much lower on the 500v ce. furthermore, it is visible that due to the differences in the e off behavior , it is possible to reduce the switching losses in comparison to the sta n dard mosfet both in hard switching dcm mode pfc and soft switching / resona n t topologies where th e turn - off losses are dominant. especially at higher loads it is visible that the reduction to for example 4 ? r g,ext brings you about 5 j lower e off . 4.2 hard commutation on conducting body diode higher s witching speeds could also cause drawbacks in case of , for example , high di/dt which could provoke high voltage peaks during hard commutation on a conducting body diode. the following figure represents this voltage peaks in comparison to a comparable stand ard mosfet at hard commutation followed after 2 s body diode conduction time ( under normal operation conditions you will not find longer body diode conduction times than 400ns ) . 0 2 4 6 8 10 12 14 0 5 10 15 20 25 30 35 e off [j] r g,ext [ ? ] e off - ipa50r500ce vs. standard mosfet i d =2.93a; t c =25 c ipa50r500ce standard mosfet 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 e on [j] r g,ext [ ? ] e on - ipa50r500ce vs. standard mosfet i d =2.93a; t c =25 c ipa50r500ce standard mosfet 0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 e off [j] r g,ext [ ? ] e off - ipa50r500ce vs. standard mosfet i d =5.85a; t c =25 c ipa50r500ce standard mosfet 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 e on [j] r g,ext [ ? ] e on - ipa50r500ce vs. standard mosfet i d =5.85a; t c =25 c ipa50r500ce standard mosfet
500v coolmos tm ce 16 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 10 : hard commutation on conduction body d iode it is shown in figure 10 that the maximum v ds has lower or the same values as the slower standard mos. in other words the 500v ce has the same or , even better, b ehavior than the comparable standard mosfet due to the self - limiting dv/dt behavior of this sj mosfet family . these two measurements and the technology parameters show that the 500v ce brings benefit s in hard switching topologies an d in sof t switching topologies. the following chapter will represent an import ant design guideline for using these sj mosfets. 5 design guideline for u sing 500v ce 5.1 minimum external gate resistor (r g,ext ) the r g,int (internal gate resistor) is defined in the datasheets nevertheless it is recommended to use an r g,ext (external gate resistor) with a value higher than 2 ? . 5.2 parallel ing of 500v ce for paralleling 500v ce , the use of ferrite beads on the gate or separate totem poles is generally recommended. 400 410 420 430 440 450 460 470 480 490 500 0 1 2 3 4 5 6 7 v ds,max , maximum v ds due to high di rr /dt [v] i f , forward current through body diode [a] ipp50r500ce vs. standard mos hard commutation on conducting body diode; half bridge configuration; high side mos = low side mos; same r g,sum =5 ? ipp50r500ce standard mos
500v coolmos tm ce 17 application note an 20 12 - 04 v 1 . 0 april 20 12 5.3 safe operation after protection mode this chapter is going to describe one design guideline which should be followed as a safety precaution. this guide should be followed when using the 500v ce in a llc topology in combination with a controller with auto - restart after any kind of pr otection ( over voltage protection ( ovp ) , over current protection ( ocp ) , over power protection ( opp ) , etc . ). if the controller is used in the application with a complete latch - off protection (system has to be manually restarted) this guideline is not appli cable . in order to provide safe operation the pause time between occurring of a protection state and auto - restart (in this document named as pause time t p _ restart ) should be set with respect to the following equation . ( 2 ) p_restart in correspondence of the gate signal. ? ? f s r restart p v i h l t ? ? ? ? 5 . 0 5 _ ? restart p t _ ? ? s ? r l ? ? h ? s i ? ? a f v ? ? v
500v coolmos tm ce 18 application note an 20 12 - 04 v 1 . 0 april 20 12 figure 11 : simplified circuitry for llc half bridge and corresponding gate drive signal with auto - restart last but not least the next chapter is going to illustrate the 500v coolmos tm ce naming system and product portfolio.
500v coolmos tm ce 19 application note an 20 12 - 04 v 1 . 0 april 20 12 6 portfolio 500v coolmos tm c e series follows the same naming guidelines as already established with the cp series e.g. ip p50 r 500 c e : i figure 12 : portfolio 500v coolmos tm ce series
500v coolmos tm ce 20 application note an 20 12 - 04 v 1 . 0 april 20 12 7 references [1] t. fujihira: theory of semiconductor superjunction devices, jpn. j. appl. phys., vol.36, pp. 6254 - 6262, 1997 [2] a.w. ludikhuize: a review of the resurf technology, proc. ispsd 2000, pp. 11 - 18 [3] x. b. chen and c. hu, optimum doping profile of power mosfets epitaxial layer., ieee trans. electron devices, vol. ed - 29, pp. 985 - 987, 1982 [4] g. deboy, f. dahlquist, t. reiman and m. scherf: latest generation of superjunction power mosfets permits the use of hard - switching topologies for high power applications, proceedings of pcim nrnberg, 2005, pp. 38 - 40 [5] g. deboy, l. lin, r. wu: coolmos tm c6 mastering the art of slowness, application note revision 1.0 2009 - 12 - 21, pp. 5 - 6 [6] ifx: coolmos tm 900v C new 900v class for superjunction devices C a new horizon for smps and renewable energy applications, applicat ion note revision 1.0 2008 - 02, pp. 6, f igure 1 [7] dr. h. kapels: superjunction mos devices C from device development towards system optimization, paper epe 2009 C barcelona, isbn 9789075815009, pp. 3

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